#1632 - SoC Physical Design Engineer (Junior and Senior)
|Job Title||SoC Physical Design Engineer (Junior and Senior)|
|Job Description||Job Description
• Performs all aspects of the SoC/ASIC/IP design flow from synthesis, place and route, timing and power to create a design database that is ready for manufacturing
The candidate must also possess strong initiative, good communication and analytical/problem solving skills, team player and be able to work within a diverse team environment
Training: technical and non-technical skills 13th month of salary committed
Company activities: company trip, year-end party, team-building, birthday, happy hours, sport clubs – football, yoga, badminton, chess…, long service award, employee of the year…)
• Candidate should have worked on timing closure challenges and possess good working knowledge of interactions between timing analysis tool and PnR tool.
• The Layout/PnR stages of the flow includes block/full-chip floor-planning, block/top connectivity management, power grid design, block level LVS/DRC and timing closure.
• Candidate should have experience of static and dynamic power/IR flow and fixes.
• Knowledge of place and route DRC, analysis and fixes.
• Awareness of DFM techniques and low power implementation are desirable.
• Candidate should be well versed with shell/tool scripting for e.g. Perl, TCL etc
• The candidate must be self-motivated to seek constant improvements in the physical design methodologies
• BA/BS degree in engineering (ex. Electronic, Electrical, Information, Communication etc) or equivalent practical experience in semiconductor industry.
• 3+ years of experience in ASIC/SoC Physical Design Implementation.
Ms. Chi Nguyen